1. Field of the Invention
This invention relates to a method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate.
2. Description of the Prior Art
A method for forming 1.0 micron well CMOS/bipolar transistor assemblies for VLSI circuits is described, for example, in an article by Miyamoto et al in IEDM 1983, Technical Digest (December 1983) pages 63 through 66. A buried collector is employed for diminishing the collector resistance, the buried collector being connected by means of a deep collector contact.
In the manufacture of this known transistor arrangement, a collector with a highly doped contact region is generated by means of a series of process steps. Due to the annealing process for generating the deep collector contact, which is performed after the LOCOS process for producing an insulating oxide for separating the active transistor regions, a temperature load is provided which has a disadvantageous effect on the component structures. A lateral parasitic substrate-pnp also arises which, among other things, increases the latch-up feedback susceptibility.